[P4-dev] General question on P4
michaelbor at gmail.com
Thu Apr 6 21:37:14 EDT 2017
I'm not confusing hardware with the language... What I mean is that P4 +
ASIC that supports it claims to give us programmable data-plane and this is
claimed to be the innovation. But that is exactly the purpose of NPUs - to
give us programmable data-plane and NPUs are around for a very long time.
So maybe I'm missing the point of innovation that P4 + ASIC that supports
it gives. As Nate said, and I agree, one big advantage is portability and
the other - ability to do verification.
So, P4 brings kind of an open standard for programmable ASICs which is
analogous to a programming language (e.g., C) for regular CPUs. While each
NPU currently have its own language and a programming style.
What do you think?
On Thu, Apr 6, 2017 at 2:07 PM, Remy Chang <remy at barefootnetworks.com>
> Hi Michael,
> It seems you're conflating hardware with language. NPU, programmable
> ASIC, general purpose CPU, and even GPU can all potentially execute p4
> On Apr 6, 2017 10:57, "Michael Borokhovich" <michaelbor at gmail.com> wrote:
> Thanks for the reply Nate!
> So, to summarize, the benefits of P4 approach are: portability and
> performance. Other than that you probably can achieve the same (if not
> better) flexibility/programmability with an NPU. Is this correct?
> On Thu, Apr 6, 2017 at 1:01 AM, Nate Foster <jnfoster at cs.cornell.edu>
>> Your question seems to be more about the relative merits of various
>> architectures than the P4 language. But yes an ASIC is generally more
>> efficient than an NPU, at least at scale.
>> Beyond efficiency there are other benefits to expressing a data plane
>> algorithm in an open framework like P4. For example, a P4 programs should
>> be relatively easy to port to a different target. The same is unlikely to
>> be true for C programs written against closed SDKs.
>> On Wed, Apr 5, 2017 at 6:59 PM, Michael Borokhovich <michaelbor at gmail.com
>> > wrote:
>>> P4 allows for configurable data-plane, e.g., we can easily support new
>>> custom protocols. However, the same functionality may be achieved by using
>>> a network processor, e.g., EZchip (the one I had experience with).
>>> As I understand, the advantages of programmable ASIC/FPGA that supports
>>> P4 is better performance and a lower price than a network processor?
>>> What do you think?
>>> P4-dev mailing list
>>> P4-dev at lists.p4.org
> P4-dev mailing list
> P4-dev at lists.p4.org
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