[P4-dev] P4 on NetFPGA Virtex 5 [Kintex-7]

KURSAT GOL kursat.gol at oeee.web.tr
Wed Dec 27 17:30:44 EST 2017


Hi Bryan,

Thank you for your kindly answer. I have got an other question like 
Sachin. I think many people are waiting this answer from you and p4-dev 
community.

Is there any way and existing codes to develop P4 projects on 
NetFPGA-1G-CML board? NetFPGA-SUME board is also very expensive for many 
students and NetFPGA-1G-CML is cheapest than SUME. Could you please 
explain this Vivado-SDNET vs. Kintex-7 logic?

@p4-dev community,

If possible is there any existing working group or project for P4 on 
NetFPGA-1G-CML borad? Could you please comment this important issue from 
your side?

Regards.

kursat


On 28.12.2017 00:29, KURSAT GOL wrote:
>
> Hi Bryan,
>
> Thank you for your kindly answer. I have got an other question like 
> Sachin. I think many people are waiting this answer from you and 
> p4-dev community.
>
> Is there any way and existing codes to develop P4 projects on 
> NetFPGA-1G-CML board? NetFPGA-SUME board is also very expensive for 
> many students and NetFPGA-1G-CML is cheapest than SUME. Could you 
> please explain this Vivado-SDNET vs. Kintex-7 logic?
>
> @p4-dev community,
>
> If possible is there any existing working group or project for P4 on 
> NetFPGA-1G-CML borad? Could you please comment this important issue 
> from your side?
>
> Regards.
>
> kursat
>
>
> On 14.12.2017 02:06, Bryan Lozano wrote:
>>
>> Sachin,
>>
>> P4 development on Xilinx FPGAs requires the use of “Xilinx SDNet”.
>>
>> SDNet generates encrypted Verilog / systemVerilog, and makes use of 
>> some Xilinx Programmable Macros for FIFOs which were not supported in 
>> the Virtex5 days.
>>
>> Getting SDNet to work with V5 would likely be a painful, time wasting 
>> development hurdle. In fact it may be impossible without direct 
>> support from Xilinx.
>>
>> I strongly urge you to move towards investing in NetFPGA-SUME (Virtex 
>> 7 FPGA). In theory you could also use any 28nm, 20nm, or 16nm 
>> development board from Xilinx/Avnet provided that it has networking 
>> interfaces.
>>
>> Here is the link for SDNet:
>>
>> https://www.xilinx.com/products/design-tools/software-zone/sdnet.html#download
>>
>> Regards,
>>
>> Bryan Lozano
>>
>> Strategic Applications Engineer
>>
>> xilinx-logo
>>
>> Email: bryanloz at xilinx.com <mailto:bryanloz at xilinx.com>
>>
>> Phone: 408.596.6205
>>
>> *From:*cl-netfpga-sume-beta-bounces at lists.cam.ac.uk 
>> [mailto:cl-netfpga-sume-beta-bounces at lists.cam.ac.uk] *On Behalf Of 
>> *Sachin Birajdhar
>> *Sent:* Wednesday, December 13, 2017 11:59 AM
>> *To:* cl-netfpga-sume-beta at lists.cam.ac.uk
>> *Subject:* P4 on NetFPGA Virtex 5
>>
>> Hi Everyone,
>>
>> I am new to NetFPGA and wanted to write P4 code on Virtex-5, so 
>> wanted to know which compiler to choose and currently I am using 
>> CentOS. I also wanted to know which OS would be preferred for 
>> NetFPGA. The idea is to use P4 language to write code on NetFPGA and 
>> currently I have my virtex-5 board attached to PC on PCI bus. Any 
>> suggestions and information would be really helpful.
>>
>> Best Regards,
>>
>> Sachin A Birajdhar
>>
>>
>>
>> _______________________________________________
>> cl-netfpga-sume-beta mailing list
>> cl-netfpga-sume-beta at lists.cam.ac.uk
>> https://lists.cam.ac.uk/mailman/listinfo/cl-netfpga-sume-beta
>

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