[P4-dev] Does P4 imply a specific programming model ?
chuck.ashley4 at gmail.com
Sun Oct 15 23:55:31 EDT 2017
I am new to this group and very excited about P4 ideas and the change it
may drive to hardware.
I have a question about the programming model assumptions P4 makes, if any.
Does P4 assume/dictate any specific target device architecture?
Is there a "standard" P4 library structure that P4 implies / provides as a
public reference implementation (not only for software simulators but also
for real hardware targets)?
Are P4 programs written in feature split or in pipeline stage split?
In my view, feature split is analogous to a run to completion model that is
probably suitable to run on NICs NPUs, while per-stage split is analogous
to a traditional pipeline programming model and probably matches how P4
will describe high capacity switches that are pipelined because that is how
they are architected.
While the feature programming model for switches may be novel, it also may
be very brittle when applied to pipeline architecture and limit how
creative customers can become.
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