[P4-dev] PSA architecture
vladimir.gurevich at barefootnetworks.com
Sun Feb 17 11:42:15 EST 2019
The short answer is "no", because it is not the job of any P4 architecture
to describe how execution is performed. The execution order is mandated by
P4 spec itself and it is always sequential (
However, many high-speed hardware targets do, indeed, support parallel
execution. The compilers for these targets are thus responsible for
identifying sections of P4 code that could be executed in parallel without
any detriment to the semantics, such as:
a = b + c;
d = c + e;
and parallelize them accordingly. Each hardware target is probably
different in terms of what it can and cannot do in parallel.
In terms of BMv2, it executes P4 program sequentially and I seriously doubt
it will do things in parallel in the foreseeable future (if ever).
Moreover, I do not believe that the current version of P4 compiler for BMv2
is capable of identifying parallelizable code in the first place.
*Vladimir Gurevich**Barefoot Networks*
*Director, Customer Training and Education*
Email: vgurevich at barefootnetworks.com
Phone: (408) 833-4505
On Sun, Feb 17, 2019 at 7:33 AM Garegin Grigoryan (RIT Student) <
gg5996 at rit.edu> wrote:
> Good morning,
> Does PSA architecture imply parallel matching of the tables in the ingress
> If so, is it going to be supported in the bmv2 virtual switch?
> Thank you.
> Garegin Grigoryan
> P4-dev mailing list
> P4-dev at lists.p4.org
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